1. Field of the Invention
The present invention relates to a circuit substrate having a first substrate that is loaded with circuit elements on a first surface thereof and a second substrate that is loaded with the first substrate, and electronic equipment that is loaded with the circuit substrate and is formed on the circuit substrate.
2. Description of the Related Art
Noise reduction elements for reducing noises between a power source and the ground are provided in the vicinity of a semiconductor chip that is loaded onto a board such as a mother board and a daughter board.
FIG. 1 is a view typically showing a conventional example in which a semiconductor chip is loaded onto a mother board.
According to the conventional example shown in FIG. 1, first, a substrate 80 is prepared in addition to a mother board 70, and a semiconductor chip 60 is mounted on a surface 80a of the additionally prepared substrate 80 and in addition noise reduction elements 90 are disposed around the mounted semiconductor chip 60, but the semiconductor chip 60 is not mounted directly on a surface 70a of the mother board 70. On a back surface 80b of the substrate 80, there is formed a large number of pads (not illustrated). And at the position of the back surface 80b, wherein the respective pad is formed, there is provided a soldering ball 81. On the other hand, also on the surface 70a of the mother board 70, as shown in FIG. 1 indicating part of the mother board 70, there is formed a large number of pads 71. Further, on the surface 70a of the mother board 70 there are provided soldering resists 72 each between the mutually adjacent pads 71.
In FIG. 1, as well as in FIG. 2 which will be later described, for the sake of the better understanding of the soldering balls 81 and the pads 71 on the surface 70a of the mother board 70, there are shown the soldering balls 81 and the pads 71 with enlargement and reducing the number of those elements. Further, while the semiconductor chip 60 mounted on the substrate 80 is packaged, FIG. 1 and FIG. 2 show the surface 80a of the substrate 80 removing a package member.
The substrate 80, on which the semiconductor chip 60 is mounted, is electronically connected with the mother board 70, when the soldering balls 81 are heated so that their pads are soldered. FIG. 1 shows a state before the soldering is carried out.
By the way, in order to enhance a noise reduction factor due to noise reduction elements, it is effective that the noise reduction elements are disposed in the vicinity of a semiconductor chip as closer as possible, or that the noise reduction elements are disposed as much as possible.
When the noise reduction elements are disposed on a board, if it is intended that a large number of noise reduction elements are disposed, it would undesirably involve a cost up and large-sizing of a board. Thus, it is tried that a noise reduction factor is enhanced with a small number of noise reduction elements. For example, as shown in FIG. 2, there is raised an example in which noise reduction elements are disposed in the vicinity of a semiconductor chip as closer as possible.
FIG. 2 is a view typically showing another conventional example in which a semiconductor chip is loaded onto a mother board.
A different point of the example shown in FIG. 2 from the example shown in FIG. 1 is that the noise reduction elements 90 are disposed on the back surface 80b of the substrate 80 on which the semiconductor chip 60 is mounted, but not on the surface 80a. Japanese Patent Publication TokuKai. 2001-144246 (pages 3–4, FIG. 1 and FIG. 2) discloses such a technology that the noise reduction elements 90 are disposed on the back surface 80b of the substrate 80.
The noise reduction elements 90 shown in FIG. 2 are disposed in an area S on the back surface 80b of the substrate 80, in which the semiconductor chip 60 is mounted on the surface 80a. On the back of the semiconductor chip 60, there are arranged several thousands of connection terminals at close intervals. When the semiconductor chip 60 is mounted on the substrate 80, the connection terminals of the back of the semiconductor chip 60 are electronically connected with the surface 80a of the substrate 80. According to the example shown in FIG. 2, the noise reduction elements 90 are located just below the connection terminals of the semiconductor chip 60, and thus are disposed nearer the semiconductor chip 60 as compare with the example shown in FIG. 1. Accordingly, the noise reduction factor by the noise reduction elements 90 shown in FIG. 2 will be enhanced.
However, an increment of the operating speed of the semiconductor chip needs further reduction of noises without an increment of the number of noise reduction elements.
By the way, an electric power is supplied via the mother board 70 to the semiconductor chip 60 which is mounted on the surface 80a of the substrate 80. That is, the electric power is supplied to the semiconductor chip 60 through the mother board 70, the soldering balls 81, and the substrate 80, in the named order. A large number of pads formed on the back surface 80b of the substrate 80 include a power pad connected to a power terminal, and a ground pad connected to a ground terminal, of the mounted semiconductor chip 60. In the event that the power pad is apart from the semiconductor chip 60, or the ground pad is apart from the semiconductor chip 60, it will cause large noises to be generated while the electric power is supplied to the semiconductor chip 60. In case of the example shown in FIG. 2, a power supply path to the semiconductor chip is elongated. Thus, this involves a possibility that it is difficult to reduce noises to a sufficient level, while a disposition of the noise reduction elements 90 nearer the semiconductor chip 60 as compared with the example shown in FIG. 1 makes it possible to enhance the noise reduction factor by the noise reduction elements 90.